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MCP3201
2.7V 12-Bit A/D Converter with SPI(R) Serial Interface
FEATURES
* * * * * * * * * * 12-bit resolution 1 LSB max DNL 1 LSB max INL (MCP3201-B) 2 LSB max INL (MCP3201-C) On-chip sample and hold SPI(R) serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 100ksps max. sampling rate at VDD = 5V 50ksps max. sampling rate at VDD = 2.7V Low power CMOS technology - 500nA typical standby current, 2A max. - 400A max. active current at 5V * Industrial temp range: -40C to +85C * 8-pin PDIP, SOIC and TSSOP packages
PACKAGE TYPES
PDIP
VREF IN+ IN- VSS 1 2 3 4 8 7 6 5 VDD CLK DOUT CS/SHDN
MCP3201
SOIC, TSSOP
VREF IN+ IN- VSS
1 2 3 4
8 7 6 5
MCP3201
VDD CLK DOUT CS/SHDN
APPLICATIONS
* * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems
FUNCTIONAL BLOCK DIAGRAM
VREF VDD VSS
DESCRIPTION
The Microchip Technology Inc. MCP3201 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The device provides a single pseudo-differential input. Differential Nonlinearity (DNL) is specified at 1 LSB, and Integral Nonlinearity (INL) is offered in 1 LSB (MCP3201-B) and 2 LSB (MCP3201-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of sample rates of up to 100ksps at a clock rate of 1.6MHz. The MCP3201 operates over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby and active currents of only 500nA and 300A, respectively. The device is offered in 8-pin PDIP, TSSOP and 150mil SOIC packages.
DAC Comparator IN+ INSample and Hold Control Logic 12-Bit SAR
Shift Register
CS/SHDN
CLK
DOUT
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 1
MCP3201
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
NAME FUNCTION +2.7V to 5.5V Power Supply Ground Positive Analog Input Negative Analog Input Serial Clock Serial Data Out Chip select/Shutdown Input Reference Voltage Input
VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied......-65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins ...................................> 4kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VDD VSS IN+ INCLK DOUT CS/SHDN VREF
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 100ksps and fCLK = 16*fSAMPLE unless otherwise noted. PARAMETER Conversion Rate Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Reference Input Voltage Range Current Drain Analog Inputs Input Voltage Range (IN+) Input Voltage Range (IN-) Leakage Current Switch Resistance Sample Capacitor RSS CSAMPLE INVSS-100 0.001 1K 20 VREF+INVSS+100 1 V mV A pF See Figure 4-1 See Figure 4-1 0.25 100 .001 VDD 150 3 V A A Note 2 CS = VDD = 5V -82 72 86 dB dB dB VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz INL DNL 12 0.75 1 0.5 1.25 1.25 1 2 1 3 5 bits LSB LSB LSB LSB LSB MCP3201-B MCP3201-C No missing codes over temperature tCONV tSAMPLE fSAMPLE 1.5 100 50 12 clock cycles clock cycles ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
DS21290B-page 2
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 100ksps and fCLK = 16*fSAMPLE unless otherwise noted. PARAMETER Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (all inputs/outputs) Timing Parameters Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements Operating Voltage Operating Current Standby Current VDD IDD IDDS 2.7 300 210 0.5 5.5 400 2 V A A A VDD = 5.0V, DOUT unloaded VDD = 2.7V, DOUT unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tDO tEN tDIS tCSH tR tF 625 100 100 312 312 100 200 200 100 1.6 0.8 MHz MHz ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 (Note 1) See Test Circuits, Figure 1-2 (Note 1) See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 (Note 1) VDD = 5V (Note 3) VDD = 2.7V (Note 3) VIH VIL VOH VOL ILI ILO CIN, COUT -10 -10 4.1 0.4 10 10 10 Straight Binary 0.7 VDD 0.3 VDD V V V V A A pF IOH = -1mA, VDD = 4.5V IOL = 1mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Note 1: This parameter is guaranteed by characterization and not 100% tested. 2: See graph that relates linearity performance to VREF level. 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 3
MCP3201
tCSH CS tSUCS tHI CLK tEN HI-Z tDO tR DOUT NULL BIT MSB OUT tF LSB HI-Z tDIS tLO
FIGURE 1-1:
Serial Timing.
Load circuit for tR, tF, tDO
1.4V
Load circuit for tDIS and tEN
Test Point VDD
tDIS Waveform 2
VDD/2
3K DOUT
Test Point DOUT
3K 100pF
tEN Waveform tDIS Waveform 1
CL = 100pF
VSS
Voltage Waveforms for tR, tF
VOH VOL
Voltage Waveforms for tEN
DOUT
CS 1 CLK DOUT 2 3 4 B11
tR
tF
tEN Voltage Waveforms for tDO
CS
CLK
Voltage Waveforms for tDIS
VIH 90% TDIS DOUT Waveform 2 10%
tDO
DOUT
DOUT Waveform 1*
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control.
FIGURE 1-2:
Test Circuits.
DS21290B-page 4
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25
Positive INL
2.0 1.5 INL (LSB) 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0
V DD = V REF = 2.7V
INL (LSB)
Positive INL
Negative INL
Negative INL
50
75
100
125
150
0
20
40
60
80
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1: Rate.
Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V).
2.0 1.5 1.0
2.0 1.5 1.0
Positive INL VDD = 2.7V F SAMPLE = 50ksps
INL (LSB)
INL (LSB)
Positive INL
0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 1 2 3 4 5
Negative INL
0.5 0.0 -0.5 -1.0 -1.5 -2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Negative INL
VREF (V)
VREF (V)
FIGURE 2-2:
Integral Nonlinearity (INL) vs. VREF.
FIGURE 2-5: (VDD = 2.7V).
Integral Nonlinearity (INL) vs. VREF
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
VDD = VREF = 2.7V FSAMPLE = 50ksps
INL (LSB)
INL (LSB)
Digital Code
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 5
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative INL Positive INL
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative INL VDD = VREF = 2.7V F SAMPLE = 50ksps Positive INL
INL (LSB)
INL (LSB)
Temperature (C)
Temperature (C)
FIGURE 2-7: Temperature.
Integral
Nonlinearity
(INL)
vs.
FIGURE 2-10: Integral Nonlinearity Temperature (VDD = 2.7V).
(INL)
vs.
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25
2.0 1.5 1.0
Positive DNL
V DD = V REF = 2.7V
DNL (LSB)
DNL (LSB)
0.5 0.0 -0.5 -1.0 -1.5 -2.0
Positive DNL
Negative DNL
Negative DNL
50
75
100
125
150
0
20
40
60
80
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V).
3.0 2.0
3.0
VDD = 2.7V
2.0
FSAMPLE = 50ksps Positive DNL
DNL (LSB)
DNL (LSB)
1.0 0.0 -1.0 -2.0 -3.0
Negative DNL
1.0 0.0
Positive DNL
Negative DNL
-1.0 -2.0 0 1 2 3 4 5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
VREF(V)
FIGURE 2-9: VREF.
Differential Nonlinearity (DNL) vs.
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V).
DS21290B-page 6
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
VDD = VREF = 2.7V FSAMPLE = 50ksps
DNL (LSB)
Digital Code
DNL (LSB)
Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V).
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative DNL
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative DNL VDD = VREF = 2.7V FSAMPLE = 50ksps Positive DNL
DNL (LSB)
DNL (LSB)
Positive DNL
Temperature (C)
Temperature (C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.
FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V).
5 4 3 2 1 0
VDD = 5V VDD = 2.7V FSAMPLE = 50ksps
20 18
Offset Error (LSB)
Gain Error (LSB)
16 14 12 10 8 6 4 2 0
VDD = 5V FSAMPLE = 100ksps
VDD = 2.7V F SAMPLE = 50ksps
-1 -2 0
FSAMPLE = 100ksps
1
2
3
4
5
0
1
2
3
4
5
VREF(V)
VREF (V)
FIGURE 2-15: Gain Error vs. VREF.
FIGURE 2-18: Offset Error vs. VREF.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 7
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
VDD = VREF = 5V FSAMPLE = 100ksps
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100
VDD = VREF = 2.7V FSAMPLE = 50ksps
Offset Error (LSB)
Gain Error (LSB)
VDD = VREF = 2.7V FSAMPLE = 50ksps
VDD = VREF = 5V FSAMPLE = 100ksps
Temperature (C)
Temperature (C)
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-22: Offset Error vs. Temperature.
100 90 80 70 60 50 40 30 20 10 0 1 10 100
VDD = VREF = 2.7V FSAMPLE = 50ksps VDD = VREF = 5V FSAMPLE = 100ksps
100 90 80
VDD = VREF = 5V FSAMPLE = 100ksps
SINAD (dB)
SNR (dB)
70 60 50 40 30 20 10 0 1 10 100
VDD = VREF = 2.7V FSAMPLE = 50ksps
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency.
FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency.
0 -10 -20 -40 -50 -60 -70 -80 -90 -100 1 10 100
VDD = VREF = 5V FSAMPLE = 100ksps
80 70
VDD = 5V FSAMPLE = 100ksps
SINAD (dB)
THD (dB)
-30
VDD = VREF = 2.7V FSAMPLE = 50ksps
60 50 40 30 20 10 0 -40 -35 -30 -25 -20 -15 -10 -5 0
VDD = 2.7V FSAMPLE = 50ksps
Input Frequency (kHz)
Input Signal Level (dB)
FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level.
DS21290B-page 8
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25C
12.0
12.00 11.75 11.50 11.25 11.00 10.75 10.50 10.25 10.00 9.75 9.50 9.25 9.00 0.0 0.5 1.0
11.5
VDD = 5V F SAMPLE = 100ksps
ENOB (rms)
ENOB (rms)
11.0 10.5 10.0 9.5 9.0 8.5 8.0
VDD = 2.7V FSAMPLE = 50ksps
VDD = VREF = 5V FSAMPLE =100ksps VDD = VREF = 2.7V FSAMPLE = 50ksps
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
100
VREF (V)
Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) vs. VREF.
FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
100 90 80 70 60 50 40 30 20 10 0 1 10 100
VDD = VREF = 2.7V F SAMPLE = 50ksps
0
Power Supply Rejection (dB)
VDD = VREF = 5V F SAMPLE = 100ksps
-10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1000 10000
SFDR (dB)
Input Frequency (kHz)
Ripple Frequency (kHz)
FIGURE 2-26: Spurious Free (SFDR) vs. Input Frequency.
Dynamic
Range
FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10000 20000 30000
VDD = VREF = 5V F SAMPLE = 100ksps
Amplitude (dB)
40000
50000
Amplitude (dB)
F INPUT = 9.985kHz 4096 points
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 10000 15000
VDD = VREF = 2.7V FSAMPLE = 50ksps FINPUT = 998.76Hz 4096 points
20000
25000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input (Representative Part).
FIGURE 2-30: Frequency Spectrum of 1kHz input (Representative Part, VDD = 2.7V).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 9
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25C
500 450 400 350
VREF = VDD All points at F CLK = 1.6MHz except at VREF = VDD = 2.5V, FCLK = 800kHz
100 90 80 70
VREF = VDD All points at FCLK = 1.6MHz except at VREF = VDD = 2.5V, FCLK = 800kHz
IREF (A)
IDD (A)
300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
FIGURE 2-31: IDD vs. VDD.
FIGURE 2-34: IREF vs. VDD.
400 350 300
VDD = VREF = 5V
100 90 80 70
VDD = VREF = 5V
IREF (A)
IDD (A)
250 200 150 100 50 0 10 100 1000 10000
VDD = VREF = 2.7V
60 50 40 30 20 10 0 10 100 1000 10000
VDD = VREF = 2.7V
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency.
FIGURE 2-35: IREF vs. Clock Frequency.
400 350 300
VDD = VREF = 5V F CLK = 1.6MHz
100 90 80 70
VDD = VREF = 5V FCLK = 1.6MHz
IDD (A)
250 200 150 100 50 0 -50 -25 0 25 50 75 100
VDD = VREF = 2.7V F CLK = 800kHz
IREF (A)
60 50 40 30 20 10 0 -50 -25 0 25 50 75 100
VDD = VREF = 2.7V FCLK = 800kHz
Temperature (C)
Temperature (C)
FIGURE 2-33: IDD vs. Temperature.
FIGURE 2-36: IREF vs. Temperature.
DS21290B-page 10
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25C
Analog Input Leakage (nA)
80 70 60
VREF = CS = VDD
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD = VREF = 5V FCLK = 1.6Mhz
IDDS (pA)
50 40 30 20 10 0
-50
-25
0
25
50
75
100
VDD (V)
Temperature (C)
FIGURE 2-37: IDDS vs. VDD.
FIGURE 2-39: Analog Input Leakage Current vs. Temperature.
100.00
VDD = VREF = CS = 5V
10.00
IDDS (nA)
1.00
0.10
0.01 -50 -25 0 25 50 75 100
Temperature (C)
FIGURE 2-38: IDDS vs. Temperature.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 11
MCP3201
3.0
3.1
PIN DESCRIPTIONS
IN+
Positive analog input. This input can vary from IN- to VREF + IN-.
In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance increases the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601, which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. If the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above Vss, then the FFFh code will not be seen unless the IN+ input level goes above VREF level.
3.2
IN-
Negative analog input. This input can vary 100mV from VSS.
3.3
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions.
3.4
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed.
4.2
Reference Input
3.5
DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.
The reference input (VREF) determines the analog input voltage range and the LSB size, as shown below.
LSB Size = VREF 4096
As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is a function of the analog input signal and the reference input as shown below.
4.0
DEVICE OPERATION
The MCP3201 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock after CS has been pulled low. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100ksps are possible on the MCP3201. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface.
Digital Output Code = 4096 * VIN VREF
where:
VIN = analog input voltage = V(IN+) - V(IN-) VREF = reference voltage
When using an external voltage reference device, the system designer should always refer to the manufacturer's recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D Converter.
4.1
Analog Inputs
The MCP3201 provides a single pseudo-differential input. The IN+ input can range from IN- to VREF (VREF +IN-). The IN- input is limited to 100mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1.
DS21290B-page 12
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
VDD VT = 0.6V Sampling Switch SS RSS = 1k CSAMPLE = DAC capacitance = 20 pF VSS
Legend VA = Signal Source RS = Source Impedance CHx = Input Channel Pad CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions SS = Sampling Switch RSS = Sampling Switch Resistor CSAMPLE = Sample/Hold Capacitance
RS
CHx CPIN 7pF
VA
VT = 0.6V
ILEAKAGE 1nA
FIGURE 4-1:
Analog Input Model.
1.8
Clock Frequency (MHz)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 1000
VDD = VREF = 5V
VDD = VREF = 2.7V
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 13
MCP3201
5.0 SERIAL COMMUNICATIONS
Communication with the device is done using a standard SPI-compatible serial interface. Initiating communication with the MCP3201 begins with the CS going low. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The device will begin to sample the analog input on the first rising edge after CS goes low. The sample period will end in the falling edge of the second clock, at which time the device will output a low null bit. The next 12 clocks will output the result of the convertCYC tCSH
sion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely.
CS
tSUCS Power Down
CLK
tSAMPLE tCONV
NULL BIT
tDATA** B5 B4 B3 B2 B1 B0* HI-Z
NULL BIT
DOUT
HI-Z
B11 B10 B9
B8
B7
B6
B11 B10 B9
B8
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed by zeros indefinitely. See Figure below. ** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with MCP3201 using MSB first Format.
tCYC tCSH
CS
tSUCS Power Down
CLK
tSAMPLE tCONV
NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4
tDATA**
B5 B6 B7 B8 B9 B10 B11*
DOUT
HI-Z
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-2:
Communication with MCP3201 using LSB first Format.
DS21290B-page 14
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
6.0
6.1
APPLICATIONS INFORMATION
Using the MCP3201 with Microcontroller SPI Ports
With most microcontroller SPI ports, it is required to clock out eight bits at a time. If this is the case, it will be necessary to provide more clocks than are required for the MCP3201. As an example, Figure 6-1 and Figure 6-2 show how the MCP3201 can be interfaced to a microcontroller with a standard SPI port. Since the MCP3201 always clocks data out on the falling edge of clock, the MCU SPI port must be configured to match this operation. SPI Mode 0,0 (clock idles low) and SPI Mode 1,1 (clock idles high) are both compatible with the MCP3201. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the CLK from the microcontroller idles in the `low' state. As shown in the diagram, the MSB is clocked out of the A/D Converter on the falling edge of the third clock pulse. After the first eight clocks have been sent to the device, the microcontroller's receive buffer will contain two unknown bits
(the output is at high impedance for the first two clocks), the null bit and the highest order five bits of the conversion. After the second eight clocks have been sent to the device, the MCU receive register will contain the lowest order seven bits and the B1 bit repeated as the A/D Converter has begun to shift out LSB first data with the extra clock. Typical procedure would then call for the lower order byte of data to be shifted right by one bit to remove the extra B1 bit. The B7 bit is then transferred from the high order byte to the lower order byte, and then the higher order byte is shifted one bit to the right as well. Easier manipulation of the converted data can be obtained by using this method. Figure 6-2 shows the same thing in SPI Mode 1,1 which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock.
CS
MCU latches data from A/D Converter on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 Data is clocked out of A/D Converter on falling edges
DOUT
HI-Z
NULL B11 BIT
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
HI-Z
LSB first data begins to come out ? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1
Data stored into MCU receive register after transmission of first 8 bits
Data stored into MCU receive register after transmission of second 8 bits
FIGURE 6-1:
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D Converter on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 Data is clocked out of A/D Converter on falling edges
DOUT
HI-Z
NULL BIT B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
HI-Z
LSB first data begins to come out ? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1
Data stored into MCU receive register after transmission of first 8 bits
Data stored into MCU receive register after transmission of second 8 bits
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 15
MCP3201
6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations
When the MCP3201 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2ms (effective clock frequency of 10kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converter, refer to AN688 "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 where an op amp is used to drive the analog input of the MCP3201. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLabTM software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems." VDD
4.096V Reference
0.1F ADI REF198 1F Tant. 0.1F 10F Device 1
Device 4
Device 3 Device 2
FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths.
VREF IN+
1F
MCP3201
R1 C1 R2 C2 R3 R4 MCP601 IN-
VIN
+ -
FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3201.
FilterLab is a trademark of Microchip Technology Inc. in the U.S.A and other countries. All rights reserved.
DS21290B-page 16
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
MCP3201 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP3201 - G T /P
Package:
P = PDIP (8 lead) SN = SOIC (150 mil Body), 8 lead ST = TSSOP, 8 lead (C Grade only) I = -40C to +85C
Temperature Range: Performance Grade: Device:
B = 1 LSB INL (TSSOP not available in this grade) C = 2 LSB INL MCP3201 = 12-Bit Serial A/D Converter MCP3201T = 12-Bit Serial A/D Converter on tape and reel (SOIC and TSSOP packages only)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 17
MCP3201
NOTES:
DS21290B-page 18
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3201
NOTES:
(c) 1999 Microchip Technology Inc.
Preliminary
DS21290B-page 19
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DS21290B-page 20
(c) 1999 Microchip Technology Inc.

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